In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

Difference between revisions of "Hardware/Latte IRQs"

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m (→‎Register List: Use Processor Interface reg naming style)
(Adding IRQ sources)
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==IRQ Sources==
 
==IRQ Sources==
 +
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
 +
|- style="background-color: #ddd;"
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! IRQ
 +
! Description
 +
|-
 +
| 0 || {{hw|Starbuck Timer}}
 +
|-
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| 1 || {{hw|NAND Interface}}
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|-
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| 2 || {{hw|AES Engine}}
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|-
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| 3 || {{hw|SHA-1 Engine}}
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|-
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| 4 || {{hw|USB Host Controller}} (EHCI)
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|-
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| 5 || {{hw|USB Host Controller}} (OHCI0)
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|-
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| 6 || {{hw|USB Host Controller}} (OHCI1)
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|-
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| 7 || {{hw|SD Host Controller}}
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|-
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| 8 || {{hw|802.11 Wireless}}
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|-
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| 9 || Unknown
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|-
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| 10 || {{hw|Latte GPIOs}} (Espresso)
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|-
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| 11 || {{hw|Latte GPIOs}} (Starbuck)
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|-
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| 12 || Unknown
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|-
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| 13 || Undefined
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|-
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| 14 || Undefined
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|-
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| 15 || Undefined
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|-
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| 16 || Undefined
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|-
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| 17 || Power button (reset)
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|-
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| 18 || {{hw|Drive Interface}} (DI)
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|-
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| 19 || Undefined
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|-
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| 20 || Unknown
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|-
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| 21 || Undefined
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|-
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| 22 || Undefined
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|-
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| 23 || Undefined
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|-
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| 24 || Undefined
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|-
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| 25 || Undefined
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|-
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| 26 || Undefined
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|-
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| 27 || Undefined
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|-
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| 28 || {{hw|Advanced Host Controller Interface}} (AHCI)
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|-
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| 29 || Undefined
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|-
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| 30 || {{hw|IPC}} (Espresso)
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|-
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| 31 || {{hw|IPC}} (Starbuck)
 +
|-
 +
|}
  
 
==Register List==
 
==Register List==

Revision as of 22:29, 24 October 2015

Latte IRQs
Access
EspressoPartial
StarbuckFull
Registers
Base0x0d800030, 0x0d800440
Length0x10, 0x48
Access size32 bits
Byte orderBig Endian
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IRQ Sources

IRQ Description
0 Starbuck Timer
1 NAND Interface
2 AES Engine
3 SHA-1 Engine
4 USB Host Controller (EHCI)
5 USB Host Controller (OHCI0)
6 USB Host Controller (OHCI1)
7 SD Host Controller
8 802.11 Wireless
9 Unknown
10 Latte GPIOs (Espresso)
11 Latte GPIOs (Starbuck)
12 Unknown
13 Undefined
14 Undefined
15 Undefined
16 Undefined
17 Power button (reset)
18 Drive Interface (DI)
19 Undefined
20 Unknown
21 Undefined
22 Undefined
23 Undefined
24 Undefined
25 Undefined
26 Undefined
27 Undefined
28 Advanced Host Controller Interface (AHCI)
29 Undefined
30 IPC (Espresso)
31 IPC (Starbuck)

Register List

The Latte IRQ controller has two different register blocks: a global ARM block mapped at the same address as on the Wii, and a new SMP block for each PPC core to use.

Global ARM block

Global ARM block
Address Bits Name Description
0x0d800030 32 LT_INTSR_PPC Triggered IRQs for the PPC
0x0d800034 32 LT_INTMR_PPC Allowed IRQs for the PPC
0x0d800038 32 LT_INTSR_ARM Triggered IRQs for the ARM
0x0d80003c 32 LT_INTMR_ARM Allowed IRQs for the ARM

SMP block

SMP block - PPC core 0
Address Bits Name Description
0x0d800440 32 LT_INTSR_AHBALL_PPC0 Triggered AHB (all) IRQs for PPC core 0
0x0d800444 32 LT_INTSR_AHBLT_PPC0 Triggered AHB (Latte) IRQs for PPC core 0
0x0d800448 32 LT_INTMR_AHBALL_PPC0 Allowed AHB (all) IRQs for PPC core 0
0x0d80044c 32 LT_INTMR_AHBLT_PPC0 Allowed AHB (Latte) IRQs for PPC core 0
SMP block - PPC core 1
Address Bits Name Description
0x0d800450 32 LT_INTSR_AHBALL_PPC1 Triggered AHB (all) IRQs for PPC core 1
0x0d800454 32 LT_INTSR_AHBLT_PPC1 Triggered AHB (Latte) IRQs for PPC core 1
0x0d800458 32 LT_INTMR_AHBALL_PPC1 Allowed AHB (all) IRQs for PPC core 1
0x0d80045c 32 LT_INTMR_AHBLT_PPC1 Allowed AHB (Latte) IRQs for PPC core 1
SMP block - PPC core 2
Address Bits Name Description
0x0d800460 32 LT_INTSR_AHBALL_PPC2 Triggered AHB (all) IRQs for PPC core 2
0x0d800464 32 LT_INTSR_AHBLT_PPC2 Triggered AHB (Latte) IRQs for PPC core 2
0x0d800468 32 LT_INTMR_AHBALL_PPC2 Allowed AHB (all) IRQs for PPC core 2
0x0d80046c 32 LT_INTMR_AHBLT_PPC2 Allowed AHB (Latte) IRQs for PPC core 2
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