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Hardware/Latte registers (view source)
Revision as of 09:09, 29 December 2019
, 09:09, 29 December 2019Initial fields listing for HW_IOPWRCTRL
Line 105:
Line 105:
{{rld|0x0d8001d4|32|HW_PLLUSB}}
{{rld|0x0d8001d4|32|HW_PLLUSB}}
{{rld|0x0d8001d8|32|HW_PLLUSBEXT}}
{{rld|0x0d8001d8|32|HW_PLLUSBEXT}}
−{{rld|0x0d8001dc|32|HW_IOPWRCTRL|I/O power control}}
+{{rla|0x0d8001dc|32|HW_IOPWRCTRL|I/O power control}}
{{rla|0x0d8001e0|32|HW_IOSTRCTRL0|I/O power strength control}}
{{rla|0x0d8001e0|32|HW_IOSTRCTRL0|I/O power strength control}}
{{rld|0x0d8001e4|32|HW_IOSTRCTRL1|I/O power strength control}}
{{rld|0x0d8001e4|32|HW_IOSTRCTRL1|I/O power strength control}}
Line 270:
Line 270:
|VERHI|Version
|VERHI|Version
|VERLO|Revision
|VERLO|Revision
+}}
+
+{{reg32 | HW_IOPWRCTRL | addr = 0x0d8001dc | hifields = 8 | lofields = 8 |
+|2 |2 |2 |2 |2 |2 |2 |2 |
+|? |? |R/W |R/W |R/W |R/W |R/W |? |
+| | |GPIO |GPIO |FLA |SDIO |SI | ||
+|2 |2 |2 |2 |2 |2 |2 |2 |
+|? |R/W |? |R/W |R/W |? |? |? |
+| |AI | |VI |DI | | | |
}}
}}