Difference between revisions of "Hardware/Latte IRQs"
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| Line 69: | Line 69: | ||
| 27 || Undefined | | 27 || Undefined | ||
|- | |- | ||
| − | | 28 || | + | | 28 || Unknown |
|- | |- | ||
| 29 || Undefined | | 29 || Undefined | ||
Revision as of 18:43, 14 April 2016
| Latte IRQs | |
| Access | |
|---|---|
| Espresso | Partial |
| Starbuck | Full |
| Registers | |
| Base | 0x0d800030, 0x0d800440 |
| Length | 0x10, 0x48 |
| Access size | 32 bits |
| Byte order | Big Endian |
IRQ Sources
| IRQ | Description |
|---|---|
| 0 | Starbuck Timer |
| 1 | NAND Interface |
| 2 | AES Engine |
| 3 | SHA-1 Engine |
| 4 | USB Host Controller (EHCI) |
| 5 | USB Host Controller (OHCI0) |
| 6 | USB Host Controller (OHCI1) |
| 7 | SD Host Controller |
| 8 | 802.11 Wireless |
| 9 | Unknown |
| 10 | Latte GPIOs (Espresso) |
| 11 | Latte GPIOs (Starbuck) |
| 12 | Unknown |
| 13 | Undefined |
| 14 | Undefined |
| 15 | Undefined |
| 16 | Undefined |
| 17 | Power button (reset) |
| 18 | Drive Interface (DI) |
| 19 | Undefined |
| 20 | Unknown |
| 21 | Undefined |
| 22 | Undefined |
| 23 | Undefined |
| 24 | Undefined |
| 25 | Undefined |
| 26 | Undefined |
| 27 | Undefined |
| 28 | Unknown |
| 29 | Undefined |
| 30 | IPC (Espresso) |
| 31 | IPC (Starbuck) |
Register List
The Latte IRQ controller has two different register blocks: a global ARM block mapped at the same address as on the Wii, and a new SMP block for each PPC core to use.
Global ARM block
| Global ARM block | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800030 | 32 | LT_INTSR_PPC | Triggered IRQs for the PPC |
| 0x0d800034 | 32 | LT_INTMR_PPC | Allowed IRQs for the PPC |
| 0x0d800038 | 32 | LT_INTSR_ARM | Triggered IRQs for the ARM |
| 0x0d80003c | 32 | LT_INTMR_ARM | Allowed IRQs for the ARM |
SMP block
| SMP block - PPC core 0 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800440 | 32 | LT_INTSR_AHBALL_PPC0 | Triggered AHB (all) IRQs for PPC core 0 |
| 0x0d800444 | 32 | LT_INTSR_AHBLT_PPC0 | Triggered AHB (Latte) IRQs for PPC core 0 |
| 0x0d800448 | 32 | LT_INTMR_AHBALL_PPC0 | Allowed AHB (all) IRQs for PPC core 0 |
| 0x0d80044c | 32 | LT_INTMR_AHBLT_PPC0 | Allowed AHB (Latte) IRQs for PPC core 0 |
| SMP block - PPC core 1 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800450 | 32 | LT_INTSR_AHBALL_PPC1 | Triggered AHB (all) IRQs for PPC core 1 |
| 0x0d800454 | 32 | LT_INTSR_AHBLT_PPC1 | Triggered AHB (Latte) IRQs for PPC core 1 |
| 0x0d800458 | 32 | LT_INTMR_AHBALL_PPC1 | Allowed AHB (all) IRQs for PPC core 1 |
| 0x0d80045c | 32 | LT_INTMR_AHBLT_PPC1 | Allowed AHB (Latte) IRQs for PPC core 1 |
| SMP block - PPC core 2 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800460 | 32 | LT_INTSR_AHBALL_PPC2 | Triggered AHB (all) IRQs for PPC core 2 |
| 0x0d800464 | 32 | LT_INTSR_AHBLT_PPC2 | Triggered AHB (Latte) IRQs for PPC core 2 |
| 0x0d800468 | 32 | LT_INTMR_AHBALL_PPC2 | Allowed AHB (all) IRQs for PPC core 2 |
| 0x0d80046c | 32 | LT_INTMR_AHBLT_PPC2 | Allowed AHB (Latte) IRQs for PPC core 2 |