28
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Line 3:
Line 3:
| arm = Full
| arm = Full
| base = 0x0d800030, 0x0d800440
| base = 0x0d800030, 0x0d800440
−| len = 0x10, 0x48
+| len = 0x14, 0x48
| bits = 32
| bits = 32
}}
}}
Line 121:
Line 121:
{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x|Unknown (Latte only)}}
{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x|Unknown (Latte only)}}
|}
|}
+
+== Register descriptions ==
+{{regsimple|LT_INTSR_AHBALL_PPCx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
+This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
+----
+{{regsimple|LT_INTSR_AHBLT_PPCx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
+This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
+----
+{{regsimple|LT_INTMR_AHBALL_PPCx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
+This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
+----
+{{regsimple|LT_INTMR_AHBLT_PPCx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
+This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
+----
+{{regsimple|LT_INTSR_AHBALL_ARM|addr=0x0d800470|bits=32|access=R/Z}}
+This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
+----
+{{regsimple|LT_INTSR_AHBLT_ARM|addr=0x0d800474|bits=32|access=R/Z}}
+This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
+----
+{{regsimple|LT_INTMR_AHBALL_ARM|addr=0x0d800478|bits=32|access=R/W}}
+This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+----
+{{regsimple|LT_INTMR_AHBLT_ARM|addr=0x0d80047c|bits=32|access=R/W}}
+This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.