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Hardware/Latte IRQs (view source)

Revision as of 21:30, 13 November 2016

2,423 bytes added ,  21:30, 13 November 2016
Proper IRQ documentation
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| bits = 32
 
| bits = 32
 
}}
 
}}
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The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.
 +
IOSU distinguishes interrupt sources that also existed in the Hollywood chipset (AHBALL) and new sources that are exclusive to the Latte (AHBLT).
 +
Additionally, the (emulated) Hollywood IRQ registers are still available for compat mode (vWii) and debugging.
    
==IRQ Sources==
 
==IRQ Sources==
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|- style="background-color: #ddd;"
 
|- style="background-color: #ddd;"
 
! IRQ
 
! IRQ
 +
! Type
 
! Description
 
! Description
 
|-
 
|-
−
| 0 || {{hw|Starbuck Timer}}
+
| (1 << 0) || AHBALL || Timer (Starbuck)
 +
|-
 +
| (1 << 1) || AHBALL || {{hw|NAND Interface}}
 +
|-
 +
| (1 << 2) || AHBALL || {{hw|AES Engine}}
 +
|-
 +
| (1 << 3) || AHBALL || {{hw|SHA-1 Engine}}
 +
|-
 +
| (1 << 4) || AHBALL || {{hw|USB Host Controller}} (EHCI)
 +
|-
 +
| (1 << 5) || AHBALL || {{hw|USB Host Controller}} (OHCI0)
 +
|-
 +
| (1 << 6) || AHBALL || {{hw|USB Host Controller}} (OHCI1)
 +
|-
 +
| (1 << 7) || AHBALL || {{hw|SD Host Controller}}
 +
|-
 +
| (1 << 8) || AHBALL || {{hw|802.11 Wireless}}
 +
|-
 +
| (1 << 9) || AHBALL || Undefined
 +
|-
 +
| (1 << 10) || AHBALL || {{hw|Latte GPIOs}} (Espresso)
 +
|-
 +
| (1 << 11) || AHBALL || {{hw|Latte GPIOs}} (Starbuck)
 +
|-
 +
| (1 << 12) || AHBALL || SYSPROT
 +
|-
 +
| (1 << 13) || AHBALL || Undefined
 +
|-
 +
| (1 << 14) || AHBALL || Undefined
 +
|-
 +
| (1 << 15) || AHBALL || Undefined
 +
|-
 +
| (1 << 16) || AHBALL || Undefined
 +
|-
 +
| (1 << 17) || AHBALL || Power button
 +
|-
 +
| (1 << 18) || AHBALL || Drive Interface
 +
|-
 +
| (1 << 19) || AHBALL || Undefined
 +
|-
 +
| (1 << 20) || AHBALL || EXI RTC
 +
|-
 +
| (1 << 21) || AHBALL || Undefined
 +
|-
 +
| (1 << 22) || AHBALL || Undefined
 +
|-
 +
| (1 << 23) || AHBALL || Undefined
 +
|-
 +
| (1 << 24) || AHBALL || Undefined
 +
|-
 +
| (1 << 25) || AHBALL || Undefined
 +
|-
 +
| (1 << 26) || AHBALL || Undefined
 +
|-
 +
| (1 << 27) || AHBALL || Undefined
 +
|-
 +
| (1 << 28) || AHBALL || SATA
 +
|-
 +
| (1 << 29) || AHBALL || Undefined
 +
|-
 +
| (1 << 30) || AHBALL || {{hw|IPC}} (Espresso compat)
 +
|-
 +
| (1 << 31) || AHBALL || {{hw|IPC}} (Starbuck compat)
 +
|-
 +
| (1 << 0) || AHBLT || Unknown
 
|-
 
|-
−
| 1 || {{hw|NAND Interface}}
+
| (1 << 1) || AHBLT || Unknown
 
|-
 
|-
−
| 2 || {{hw|AES Engine}}
+
| (1 << 2) || AHBLT || Unknown
 
|-
 
|-
−
| 3 || {{hw|SHA-1 Engine}}
+
| (1 << 3) || AHBLT || Unknown
 
|-
 
|-
−
| 4 || {{hw|USB Host Controller}} (EHCI)
+
| (1 << 4) || AHBLT || DRH
 
|-
 
|-
−
| 5 || {{hw|USB Host Controller}} (OHCI0)
+
| (1 << 5) || AHBLT || Unknown
 
|-
 
|-
−
| 6 || {{hw|USB Host Controller}} (OHCI1)
+
| (1 << 6) || AHBLT || Unknown
 
|-
 
|-
−
| 7 || {{hw|SD Host Controller}}
+
| (1 << 7) || AHBLT || Unknown
 
|-
 
|-
−
| 8 || {{hw|802.11 Wireless}}
+
| (1 << 8) || AHBLT || {{hw|AES Engine}} (AESS)
 
|-
 
|-
−
| 9 || Unknown
+
| (1 << 9) || AHBLT || {{hw|SHA-1 Engine}} (SHAS-1)
 
|-
 
|-
−
| 10 || {{hw|Latte GPIOs}} (Espresso)
+
| (1 << 10) || AHBLT || Unknown
 
|-
 
|-
−
| 11 || {{hw|Latte GPIOs}} (Starbuck)
+
| (1 << 11) || AHBLT || Unknown
 
|-
 
|-
−
| 12 || Unknown
+
| (1 << 12) || AHBLT || Unknown
 
|-
 
|-
−
| 13 || Undefined
+
| (1 << 13) || AHBLT || I2C (Espresso)
 
|-
 
|-
−
| 14 || Undefined
+
| (1 << 14) || AHBLT || I2C (Starbuck)
 
|-
 
|-
−
| 15 || Undefined
+
| (1 << 15) || AHBLT || Undefined
 
|-
 
|-
−
| 16 || Undefined
+
| (1 << 16) || AHBLT || Undefined
 
|-
 
|-
−
| 17 || Power button (reset)
+
| (1 << 17) || AHBLT || Undefined
 
|-
 
|-
−
| 18 || {{hw|Drive Interface}} (DI)
+
| (1 << 18) || AHBLT || Undefined
 
|-
 
|-
−
| 19 || Undefined
+
| (1 << 19) || AHBLT || Undefined
 
|-
 
|-
−
| 20 || Unknown
+
| (1 << 20) || AHBLT || Undefined
 
|-
 
|-
−
| 21 || Undefined
+
| (1 << 21) || AHBLT || Undefined
 
|-
 
|-
−
| 22 || Undefined
+
| (1 << 22) || AHBLT || Undefined
 
|-
 
|-
−
| 23 || Undefined
+
| (1 << 23) || AHBLT || Undefined
 
|-
 
|-
−
| 24 || Undefined
+
| (1 << 24) || AHBLT || Undefined
 
|-
 
|-
−
| 25 || Undefined
+
| (1 << 25) || AHBLT || Undefined
 
|-
 
|-
−
| 26 || Undefined
+
| (1 << 26) || AHBLT || {{hw|IPC}} (Espresso CPU2)
 
|-
 
|-
−
| 27 || Undefined
+
| (1 << 27) || AHBLT || {{hw|IPC}} (Starbuck CPU2)
 
|-
 
|-
−
| 28 || Unknown
+
| (1 << 28) || AHBLT || {{hw|IPC}} (Espresso CPU1)
 
|-
 
|-
−
| 29 || Undefined
+
| (1 << 29) || AHBLT || {{hw|IPC}} (Starbuck CPU1)
 
|-
 
|-
−
| 30 || {{hw|IPC}} (Espresso)
+
| (1 << 30) || AHBLT || {{hw|IPC}} (Espresso CPU0)
 
|-
 
|-
−
| 31 || {{hw|IPC}} (Starbuck)
+
| (1 << 31) || AHBLT || {{hw|IPC}} (Starbuck CPU0)
 
|-
 
|-
 
|}
 
|}
    
==Register List==
 
==Register List==
−
The Latte IRQ engine has two different register blocks: a global block compatible with the old Wii hardware (Wood), and a new SMP block split across the three Wii U's (Latte) PPC cores and the ARM core. Each core's region of the SMP block has registers equivalent to the old global block.
+
Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for compat mode (vWii) and another for normal mode (Wii U).
 +
The subset used for normal mode is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.
 +
There are also traces of additional unused registers which appear to have been used in the past for debugging purposes (ARM2x).
    
===Compat block===
 
===Compat block===
Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/2335"