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mLine 148:
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Hardware/Latte registers (view source)
Revision as of 21:41, 4 February 2016
, 21:41, 4 February 2016Proper correction
{{rla|0x0d8005a0|32|LT_ASICREV_CCR|CCR chip revision ID (Latte)}}
{{rla|0x0d8005a0|32|LT_ASICREV_CCR|CCR chip revision ID (Latte)}}
{{rla|0x0d8005a4|32|LT_DEBUG|DEBUG mode flags}}
{{rla|0x0d8005a4|32|LT_DEBUG|DEBUG mode flags}}
{{rld|0x0d8005b0|32|LT_COMPAT_MEMCTRL|Compat mode registers|drs=4}}
{{rld|0x0d8005b0|32|LT_COMPAT_MEMCTRL|Compat mode registers|drs=5}}
{{rld|0x0d8005b4|32|LT_COMPAT_AHB}}
{{rld|0x0d8005b4|32|LT_COMPAT_AHB}}
{{rld|0x0d8005b8|32|LT_COMPAT_STEREO_OUT_SELECT}}
{{rld|0x0d8005b8|32|LT_COMPAT_STEREO_OUT_SELECT}}
{{rld|0x0d8005bc|32|LT_IOP2X}}
{{rld|0x0d8005bc|32|LT_IOP2X}}
{{rld|0x0d8005c0|32|LT_RESETS2|System resets {{check}}}}
{{rld|0x0d8005c0|32|LT_COMPAT_UNK2}}
{{rld|0x0d8005c8|32|LT_IOSTRENGTH_CTRL2|Subsystems' power strength}}
{{rld|0x0d8005c8|32|LT_IOSTRENGTH_CTRL2|Subsystems' power strength}}
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
{{rld|0x0d8005e0|32|LT_SATASUBSYS|Related to the SATA subsystem}}
{{rld|0x0d8005e0|32|LT_RESETS2|System resets {{check}}}}
{{rld|0x0d8005e4|32|LT_AHMN_RESETS|Unknown}}
{{rld|0x0d8005e4|32|LT_AHMN_RESETS|Unknown}}
{{rld|0x0d8005e8|32|LT_CLOCKGATE2|Unknown}}
{{rld|0x0d8005e8|32|LT_CLOCKGATE2|Unknown}}