Changes

{{reglist|NAND Interface}}

{{reglist|NAND Interface}}

{{rla|0x0d010000|32|NAND_CTRL|NAND Control and Status}}

{{rla|0x0d010000|32|NAND_CTRL|NAND Control and Status}}

{{rla|0x0d010004|32|NAND_CONFIG|??}}

{{rla|0x0d010004|32|NAND_CONFIG|NAND configuration register}}

{{rla|0x0d010008|32|NAND_ADDR1|Address bytes 1-2 (column)}}

{{rla|0x0d010008|32|NAND_ADDR1|Address bytes 1-2 (column)}}

{{rla|0x0d01000c|32|NAND_ADDR2|Address bytes 3-5 (row)}}

{{rla|0x0d01000c|32|NAND_ADDR2|Address bytes 3-5 (row)}}

{{rla|0x0d010010|32|NAND_DATABUF|Memory address of the Data buffer}}

{{rla|0x0d010010|32|NAND_DATABUF|Memory address of the Data buffer}}

{{rla|0x0d010014|32|NAND_ECCBUF|Memory address of the Spare buffer}}

{{rla|0x0d010014|32|NAND_ECCBUF|Memory address of the Spare buffer}}

{{rla|0x0d010018|32|NAND_BANK|NAND bank swapping}}

{{rla|0x0d010018|32|NAND_BANK|NAND bank swapping (WiiU/vWii)}}

{{rld|0x0d01001c...0x0d01002c|32|NAND_UNK1|Unknown}}

{{rld|0x0d010030|32|NAND_UNK_CTRL|Unknown}}

{{rld|0x0d010030|32|NAND_UNK_STATE|Unknown}}

{{rld|0x0d010040...0x0d010100|32|NAND_UNK|Eight 0x18-sized mirrors?}}

{{rld|0x0d010034...0x0d010100|32|NAND_UNK2|Unknown}}

|}

|}

== Register Details ==

== Register Details ==

{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = 5 |

{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = 5 |