Changes

{{rld|0x0d8b080c|32|AHMN_RDBIMSK|AHMN read buffer invalidate mask}}

{{rld|0x0d8b080c|32|AHMN_RDBIMSK|AHMN read buffer invalidate mask}}

{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}

{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}

{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt state}}

{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt status}}

{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}

{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN read/write transfer state}}

{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN read/write transfer status}}

{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}

{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}

{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}

{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}