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Hardware/SEEPROM (view source)

Revision as of 23:10, 22 April 2023

214 bytes added , 23:10, 22 April 2023

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The Latte package contains a [http://www.atmel.com/images/doc0172z.pdf 93C66] (or similar) SPI EEPROM, organized as 256 16-bit words, making it twice the size of the EEPROM found in the Wii's Hollywood package. It is accessed by twiddling some of the Starbuck GPIO lines in the exact same way as it was done on the Wii's Starlet GPIO lines.

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== ~~SEEPROM~~ Contents ==

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== Contents ==

Most of the data here is written once at the factory and never changed, but some fields are updated fairly frequently:

{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"

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| 0x030 (0x18 * 2) || 0x08 bytes || OTP version name string

|-

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| 0x038 (0x1C * 2) || 0x04 bytes || BC struct's CRC32

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| 0x038 (0x1C * 2) || 0x04 bytes || BoardConfig struct's CRC32

|-

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| 0x03C (0x1E * 2) || 0x02 bytes || BC struct's available size

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| 0x03C (0x1E * 2) || 0x02 bytes || BoardConfig struct's available size

|-

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| 0x03E (0x1F * 2) || 0x02 bytes || BC library version

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| 0x03E (0x1F * 2) || 0x02 bytes || BoardConfig library version

|-

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| 0x040 (0x20 * 2) || 0x02 bytes || BC author

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| 0x040 (0x20 * 2) || 0x02 bytes || BoardConfig author

+

0x404D: @M (Atmel?)

|-

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| 0x042 (0x21 * 2) || 0x02 bytes || BC boardType

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| 0x042 (0x21 * 2) || 0x02 bytes || BoardConfig boardType

0x4346: CF (CAFE: Retail/Kiosk)

0x4354: CT (CAT: Devkit)

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0x4556: EV (EV: Evaluation board~~? EV_Y also exists~~)

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0x4556: EV (EV: Evaluation board)

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0x4944: ID

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0x4944: ID (WUIH_DEV?)

0x4948: IH (WUIH?)

|-

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| 0x044 (0x22 * 2) || 0x02 bytes || BC boardRevision

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| 0x044 (0x22 * 2) || 0x02 bytes || BoardConfig boardRevision

|-

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| 0x046 (0x23 * 2) || 0x02 bytes || BC bootSource

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| 0x046 (0x23 * 2) || 0x02 bytes || BoardConfig bootSource

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0x4E31: N1 (NAND?)

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0x5333: S3 (SDIO?)

|-

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| 0x048 (0x24 * 2) || 0x02 bytes || BC ddr3Size

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| 0x048 (0x24 * 2) || 0x02 bytes || BoardConfig ddr3Size

|-

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| 0x04A (0x25 * 2) || 0x02 bytes || BC ddr3Speed

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| 0x04A (0x25 * 2) || 0x02 bytes || BoardConfig ddr3Speed

|-

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| 0x04C (0x26 * 2) || 0x02 bytes || BC ppcClockMultiplier

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| 0x04C (0x26 * 2) || 0x02 bytes || BoardConfig ppcClockMultiplier

|-

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| 0x04E (0x27 * 2) || 0x02 bytes || BC iopClockMultiplier

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| 0x04E (0x27 * 2) || 0x02 bytes || BoardConfig iopClockMultiplier

|-

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| 0x050 (0x28 * 2) || 0x02 bytes || BC video1080p

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| 0x050 (0x28 * 2) || 0x02 bytes || BoardConfig video1080p

|-

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| 0x052 (0x29 * 2) || 0x02 bytes || BC ddr3Vendor

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| 0x052 (0x29 * 2) || 0x02 bytes || BoardConfig ddr3Vendor

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0x5521: U! (Micron?)

|-

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| 0x054 (0x2A * 2) || 0x02 bytes || BC movPassiveReset

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| 0x054 (0x2A * 2) || 0x02 bytes || BoardConfig movPassiveReset

|-

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| 0x056 (0x2B * 2) || 0x02 bytes || BC sysPllSpeed

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| 0x056 (0x2B * 2) || 0x02 bytes || BoardConfig sysPllSpeed

|-

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| 0x058 (0x2C * 2) || 0x02 bytes || BC sataDevice

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| 0x058 (0x2C * 2) || 0x02 bytes || BoardConfig sataDevice

0x0001: Default

0x0002: No device

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0x0008: GEN1-HDD (Kiosk CAT-I with HDD)

|-

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| 0x05A (0x2D * 2) || 0x02 bytes || BC consoleType

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| 0x05A (0x2D * 2) || 0x02 bytes || BoardConfig consoleType

0x0001: WUP (Retail)

0x0002: CAT-R (Test)

0x0003: CAT-DEV (Debug)

0x0004: EV board

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0x0005: Promotion (Kiosk CAT-I)

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0x0005: Promotion (Kiosk CAT-I/CAT-SES)

0x0006: OrchestraX

0x0007: WUIH

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0x0009: CAT_DEV_WUIH

|-

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| 0x05C (0x2E * 2) || 0x04 bytes || BC devicePresence

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| 0x05C (0x2E * 2) || 0x04 bytes || BoardConfig devicePresence

Always 0x00000000 in retail/kiosk units.

|-

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| 0x060 (0x30 * 2) || 0x20 bytes || Reserved for ~~BC ("~~BoardConfig~~") library~~

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| 0x060 (0x30 * 2) || 0x20 bytes || Reserved for BoardConfig

|-

| 0x080 (0x40 * 2) || 0x10 bytes || Wii U drive key

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Structure containing parameters for boot0:

- 0x1C0 to 0x1C2 (0x02 bytes): CPU control flags.

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-> Bits 0-9 set the CPU speed in MHz used for delay calculations.

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- Bits 0-9 set the CPU speed in MHz used for delay calculations.

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-> Bits 10-14 set a delay before checking if the SD boot combo has been pressed.

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- Bits 10-14 set a delay before checking if the SD boot combo has been pressed.

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-> Bit 15 causes 0x3 to be written to LT_IOP2X which increases the ARM CPU clock multiplier.

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- Bit 15 causes 0x3 to be written to LT_IOP2X which increases the ARM CPU clock multiplier.

- 0x1C2 to 0x1C4 (0x02 bytes): NAND and SD control flags.

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-> Bits 0-7 supply a custom value for the SD card clock divider.

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- Bits 0-7 supply a custom value for the SD card clock divider.

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-> Bits 8-9 set a delay before initializing the SD host controller.

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- Bits 8-9 set a delay before initializing the SD host controller.

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-> Bit 10 enables SD card 4-bit bus through CMD55 (SD_APP_CMD) and CMD6 (SD_APP_SET_BUS_WIDTH).

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- Bit 10 enables SD card 4-bit bus through CMD55 (SD_APP_CMD) and CMD6 (SD_APP_SET_BUS_WIDTH).

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-> Bit 11 enables using a supplied custom value for the SD card clock divider.

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- Bit 11 enables using a supplied custom value for the SD card clock divider.

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-> Bit 13 enables using a supplied custom value for overwriting NAND_BANK.

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- Bit 13 enables using a supplied custom value for overwriting NAND_BANK.

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-> Bit 14 enables using a supplied custom value for overwriting NAND_CONFIG.

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- Bit 14 enables using a supplied custom value for overwriting NAND_CONFIG.

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-> Bit 15 forces NAND to validate ECC data.

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- Bit 15 forces NAND to validate ECC data.

- 0x1C4 to 0x1C8 (0x04 bytes): Custom value for NAND_CONFIG (optional).

- 0x1C8 to 0x1CC (0x04 bytes): Custom value for NAND_BANK (optional).

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Changes

Hardware/SEEPROM (view source)

Revision as of 23:10, 22 April 2023

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