301
edits
Changes
no edit summary
Line 64:
Line 64:
Line 312:
Line 312:
*(u32 *)HW_AIPPROT = aip_prot_val;
*(u32 *)HW_AIPPROT = aip_prot_val;
−=== check_hw ===
+=== TestHardware ===
boot1 setups the fan's speed and power, initializes I2C for SMC and validates the hardware version.
boot1 setups the fan's speed and power, initializes I2C for SMC and validates the hardware version.
Line 163:
Line 163:
}
}
−=== get_rtc_events ===
+=== GetRtcEvents ===
boot1 setups EXI for the RTC and collects events from RTC_CONTROL0 and RTC_CONTROL1.
boot1 setups EXI for the RTC and collects events from RTC_CONTROL0 and RTC_CONTROL1.
Line 293:
Line 293:
}
}
−=== init_mem ===
+=== InitializeMemory ===
boot1 initializes the memory controller.
boot1 initializes the memory controller.
}
}
−=== mem2_test ===
+=== WriteMem2 ===
boot1 tests MEM2 by writing a pattern over it's first 0x400 bytes.
boot1 tests MEM2 by writing a pattern over it's first 0x400 bytes.
Line 357:
Line 357:
}
}
−=== mem2_check ===
+=== TestMem2 ===
boot1 checks if MEM2 refreshing is working.
boot1 checks if MEM2 refreshing is working.
Line 413:
Line 413:
}
}
−=== mem0_clear ===
+=== ClearMem0 ===
boot1 clears all MEM0 and adjusts IOP clock multiplier if necessary.
boot1 clears all MEM0 and adjusts IOP clock multiplier if necessary.
Line 445:
Line 445:
}
}
−=== get_boot_info ===
+=== GetBootInfo ===
boot1 decrypts the PRSH/PRST from MEM2 and parses the "boot_info" structure.
boot1 decrypts the PRSH/PRST from MEM2 and parses the "boot_info" structure.
Line 512:
Line 512:
sub_D40AC30(pflags_val);
sub_D40AC30(pflags_val);
−=== load_fw_img ===
+=== LoadFwImg ===
boot1 loads, validates and decrypts the IOSU fw.img file.
boot1 loads, validates and decrypts the IOSU fw.img file.