339
edits
Changes
Update registers
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=== Wood block ===
=== Wood block ===
{{reglist|Wood block}}
{{reglist|Wood block}}
−{{rla|0x0d800030|32|HW_PPCIRQFLAG|Triggered IRQs for the PPC core in vWii}}
+{{rla|0x0d800030|32|HW_PPCINTSTS|Triggered IRQs for the PPC core in vWii}}
−{{rla|0x0d800034|32|HW_PPCIRQMASK|Allowed IRQs for the PPC core in vWii}}
+{{rla|0x0d800034|32|HW_PPCINTEN|Allowed IRQs for the PPC core in vWii}}
−{{rla|0x0d800038|32|HW_ARMIRQFLAG|Triggered IRQs for the ARM core in vWii}}
+{{rla|0x0d800038|32|HW_IOPINTSTS|Triggered IRQs for the ARM core in vWii}}
−{{rla|0x0d80003c|32|HW_ARMIRQMASK|Allowed IRQs for the ARM core in vWii}}
+{{rla|0x0d80003c|32|HW_IOPIRQINTEN|Allowed IRQs for the ARM core in vWii}}
−{{rld|0x0d800040|32|HW_ARMFIQMASK|Allowed FIQs for the ARM core in vWii}}
+{{rld|0x0d800040|32|HW_IOPFIQINTEN|Allowed FIQs for the ARM core in vWii}}
|}
|}
=== Latte block ===
=== Latte block ===
{{reglist|Latte block - PPC core 0}}
{{reglist|Latte block - PPC core 0}}
−{{rla|0x0d800440|32|LT_PPCIRQFLAGALL0|Triggered IRQs for PPC core 0 (all)}}
+{{rla|0x0d800440|32|LT_PPC0INTSTSALL|Triggered IRQs for PPC core 0 (Wood and Latte)}}
−{{rla|0x0d800444|32|LT_PPCIRQFLAGLT0|Triggered IRQs for PPC core 0 (Latte only)}}
+{{rla|0x0d800444|32|LT_PPC0INTSTSLATTE|Triggered IRQs for PPC core 0 (Latte only)}}
−{{rla|0x0d800448|32|LT_PPCIRQMASKALL0|Allowed IRQs for PPC core 0 (all)}}
+{{rla|0x0d800448|32|LT_PPC0INTENALL|Allowed IRQs for PPC core 0 (Wood and Latte)}}
−{{rla|0x0d80044c|32|LT_PPCIRQMASKLT0|Allowed IRQs for PPC core 0 (Latte only)}}
+{{rla|0x0d80044c|32|LT_PPC0INTENLATTE|Allowed IRQs for PPC core 0 (Latte only)}}
|}
|}
{{reglist|Latte block - PPC core 1}}
{{reglist|Latte block - PPC core 1}}
−{{rla|0x0d800450|32|LT_PPCIRQFLAGALL1|Triggered IRQs for PPC core 1 (all)}}
+{{rla|0x0d800450|32|LT_PPC1INTSTSALL|Triggered IRQs for PPC core 1 (Wood and Latte)}}
−{{rla|0x0d800454|32|LT_PPCIRQFLAGLT1|Triggered IRQs for PPC core 1 (Latte only)}}
+{{rla|0x0d800454|32|LT_PPC1INTSTSLATTE|Triggered IRQs for PPC core 1 (Latte only)}}
−{{rla|0x0d800458|32|LT_PPCIRQMASKALL1|Allowed IRQs for PPC core 1 (all)}}
+{{rla|0x0d800458|32|LT_PPC1INTENALL|Allowed IRQs for PPC core 1 (Wood and Latte)}}
−{{rla|0x0d80045c|32|LT_PPCIRQMASKLT1|Allowed IRQs for PPC core 1 (Latte only)}}
+{{rla|0x0d80045c|32|LT_PPC1INTENLATTE|Allowed IRQs for PPC core 1 (Latte only)}}
|}
|}
{{reglist|Latte block - PPC core 2}}
{{reglist|Latte block - PPC core 2}}
−{{rla|0x0d800460|32|LT_PPCIRQFLAGALL2|Triggered IRQs for PPC core 2 (all)}}
+{{rla|0x0d800460|32|LT_PPC2INTSTSALL|Triggered IRQs for PPC core 2 (Wood and Latte)}}
−{{rla|0x0d800464|32|LT_PPCIRQFLAGLT2|Triggered IRQs for PPC core 2 (Latte only)}}
+{{rla|0x0d800464|32|LT_PPC2INTSTSLATTE|Triggered IRQs for PPC core 2 (Latte only)}}
−{{rla|0x0d800468|32|LT_PPCIRQMASKALL2|Allowed IRQs for PPC core 2 (all)}}
+{{rla|0x0d800468|32|LT_PPC2INTENALL|Allowed IRQs for PPC core 2 (Wood and Latte)}}
−{{rla|0x0d80046c|32|LT_PPCIRQMASKLT2|Allowed IRQs for PPC core 2 (Latte only)}}
+{{rla|0x0d80046c|32|LT_PPC2INTENLATTE|Allowed IRQs for PPC core 2 (Latte only)}}
|}
|}
{{reglist|Latte block - ARM core}}
{{reglist|Latte block - ARM core}}
−{{rla|0x0d800470|32|LT_ARMIRQFLAGALL|Triggered IRQs for ARM core (all)}}
+{{rla|0x0d800470|32|LT_IOPINTSTSALL|Triggered IRQs for ARM core (Wood and Latte)}}
−{{rla|0x0d800474|32|LT_ARMIRQFLAGLT|Triggered IRQs for ARM core (Latte only)}}
+{{rla|0x0d800474|32|LT_IOPINTSTSLATTE|Triggered IRQs for ARM core (Latte only)}}
−{{rla|0x0d800478|32|LT_ARMIRQMASKALL|Allowed IRQs for ARM core (all)}}
+{{rla|0x0d800478|32|LT_IOPIRQINTENALL|Allowed IRQs for ARM core (Wood and Latte)}}
−{{rla|0x0d80047c|32|LT_ARMIRQMASKLT|Allowed IRQs for ARM core (Latte only)}}
+{{rla|0x0d80047c|32|LT_IOPIRQINTENLATTE|Allowed IRQs for ARM core (Latte only)}}
−{{rld|0x0d800480|32|LT_ARMFIQMASKALL|Allowed FIQs for the ARM core (all)}}
+{{rld|0x0d800480|32|LT_IOPFIQINTENALL|Allowed FIQs for the ARM core (Wood and Latte)}}
−{{rld|0x0d800484|32|LT_ARMFIQMASKLT|Allowed FIQs for the ARM core (Latte only)}}
+{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE|Allowed FIQs for the ARM core (Latte only)}}
|}
|}
== Register descriptions ==
== Register descriptions ==
−{{regsimple|LT_PPCIRQFLAGALLx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
+{{regsimple|LT_PPCxINTSTSALL|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
----
----
−{{regsimple|LT_PPCIRQFLAGLTx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
+{{regsimple|LT_PPCxINTSTSLATTE|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
----
----
−{{regsimple|LT_PPCIRQMASKALLx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
+{{regsimple|LT_PPCxINTENALL|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
----
----
−{{regsimple|LT_PPCIRQMASKLTx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
+{{regsimple|LT_PPCxINTENLATTE|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
----
----
−{{regsimple|LT_ARMIRQFLAGALL|addr=0x0d800470|bits=32|access=R/Z}}
+{{regsimple|LT_IOPINTSTSALL|addr=0x0d800470|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
----
----
−{{regsimple|LT_ARMIRQFLAGLT|addr=0x0d800474|bits=32|access=R/Z}}
+{{regsimple|LT_IOPINTSTSLATTE|addr=0x0d800474|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
----
----
−{{regsimple|LT_ARMIRQMASKALL|addr=0x0d800478|bits=32|access=R/W}}
+{{regsimple|LT_IOPIRQINTENALL|addr=0x0d800478|bits=32|access=R/W}}
−This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
----
----
−{{regsimple|LT_ARMIRQMASKLT|addr=0x0d80047c|bits=32|access=R/W}}
+{{regsimple|LT_IOPIRQINTENLATTE|addr=0x0d80047c|bits=32|access=R/W}}
−This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.