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Hardware/Latte GPIOs (view source)

Revision as of 20:20, 2 July 2016

3,272 bytes added ,  20:20, 2 July 2016
gpio stuff
Line 3: Line 3:  
| arm = Full
 
| arm = Full
 
| ppc = Partial
 
| ppc = Partial
āˆ’
| base = 0x0d8000c0
+
| base = 0x0d8000c0, 0x0d800520
āˆ’
| len = 0x40
+
| len = 0x80
 
| bits = 32
 
| bits = 32
 
| ppcirq = None
 
| ppcirq = None
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}}
 
}}
   āˆ’
The Latte chipset includes at least 29 general purpose I/O lines with interrupt capability. Two sets of registers are provided, and the Espresso only has access to one set. This set accesses a configurable subset of the IO pins, which the Starbuck can select.
+
The Latte chipset includes two groups of general purpose I/O lines with interrupt capability. Four sets of registers are provided (two for each group), and the Espresso only has access to two sets. These sets access a configurable subset of the IO pins, which the Starbuck can select.
    
== Pin connections ==
 
== Pin connections ==
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|-  
 
|-  
 
! Bit
 
! Bit
 +
! Group
 
! Direction
 
! Direction
 
! Connection
 
! Connection
 
! Description
 
! Description
 
|-
 
|-
āˆ’
| 0 || IN || SYS_INT || Power button input (RTCSysInt, FanSpeed and/or ToucanSelect).
+
| 0 || 1 || IN || RTCSysInt || Power button input.
 
|-
 
|-
āˆ’
| 1 || OUT || DWIFI_MODE || Unknown (DWiFiMode and/or SMCI2CClock).
+
| 0 || 2 || OUT || FanSpeed || Fan speed.
 
|-
 
|-
āˆ’
| 2 || OUT || FAN_PWR || Fan power, active high (FanPower and/or SMCI2CData).
+
| 0 || 1 || I/O || ToucanSelect || "Toucan" select (devkit only).
 
|-
 
|-
āˆ’
| 3 || OUT || DC_DC || DC/DC converter power (DCDCPwrCnt, DCDCPwrCnt2 and/or CCRIO3), active high.
+
| 1 || 1 || OUT || DWiFiMode || DWiFi mode.
 
|-
 
|-
āˆ’
| 4 || OUT || AV_INT || A/V Encoder interrupt (AVInterrupt)?
+
| 1 || 2 || IN || SMCI2CClock || SMC (surface mounted components) IĀ²C Clock.
 
|-
 
|-
āˆ’
| 5 || OUT || ESP10_FIX || Unknown (ESP10WorkAround and/or CCRIO12).
+
| 2 || 1 || OUT || FanPower || Fan power, active high.
 
|-
 
|-
āˆ’
| 6 || OUT || AV_RST || A/V Encoder reset (AVReset)?
+
| 2 || 2 || IN || SMCI2CData || SMC (surface mounted components) IĀ²C Data.
 
|-
 
|-
āˆ’
| 7 || UNK || UNKNOWN || Unknown.
+
| 3 || 1 || OUT || DCDCPwrCnt || DC/DC converter power (group 1), active high.
 
|-
 
|-
āˆ’
| 8 || OUT || SDC_PWR || Unknown (SDC0S0Power and/or PADPD).
+
| 3 || 2 || OUT || DCDCPwrCnt2 || DC/DC converter power (group 2), active high.
 
|-
 
|-
āˆ’
| 9 || UNK || UNKNOWN  || Unknown.
+
| 3 || 1 || OUT || CCRIO3 || Unknown (duplicate?)
 
|-
 
|-
āˆ’
| 10 || OUT || EEPROM_CS || SEEPROM Chip Select.
+
| 4 || 1 || UNK || UNKNOWN || Unknown.
 
|-
 
|-
āˆ’
| 11 || OUT || EEPROM_SK || SEEPROM Clock.
+
| 4 || 2 || IN || AVInterrupt || A/V encoder interrupt (from Espresso).
 
|-
 
|-
āˆ’
| 12 || OUT || EEPROM_DO || Data to SEEPROM.
+
| 5 || 1 || OUT || ESP10WorkAround || Unknown.
 
|-
 
|-
āˆ’
| 13 || IN || EEPROM_DI || Data from SEEPROM.
+
| 5 || 2 || OUT || CCRIO12 || Unknown.
 
|-
 
|-
āˆ’
| 14 || OUT || AV0_I2C_CLOCK || A/V Encoder (#0) IĀ²C Clock.
+
| 6 || 1 || UNK || UNKNOWN || Unknown.
 
|-
 
|-
āˆ’
| 15 || I/O || AV0_I2C_DATA|| A/V Encoder (#0) IĀ²C Data.
+
| 6 || 2 || OUT || AVReset || A/V encoder reset (from Espresso).
 
|-
 
|-
āˆ’
| 16 || OUT || NDEV_LED || DevKit LED?
+
| 7 || 1 || UNK || UNKNOWN || Unknown.
 
|-
 
|-
āˆ’
| 17 || OUT || DEBUG1 || Debug?
+
| 8 || 1 || OUT || PADPD || Gamepad power state.
 
|-
 
|-
āˆ’
| 18 || OUT || DEBUG2 || Debug?
+
| 9 || 1 || UNK || UNKNOWN  || Unknown.
 
|-
 
|-
āˆ’
| 19 || OUT || DEBUG3 || Debug?
+
| 10 || 1 || OUT || EEPROM_CS || SEEPROM Chip Select.
 
|-
 
|-
āˆ’
| 20 || OUT || DEBUG4 || Debug?
+
| 11 || 1 || OUT || EEPROM_SK || SEEPROM Clock.
 
|-
 
|-
āˆ’
| 21 || OUT || DEBUG5 || Debug?
+
| 12 || 1 || OUT || EEPROM_DO || Data to SEEPROM.
 
|-
 
|-
āˆ’
| 22 || OUT || DEBUG6 || Debug?
+
| 13 || 1 || IN || EEPROM_DI || Data from SEEPROM.
 
|-
 
|-
āˆ’
| 23 || OUT || DEBUG7 || Debug?
+
| 14 || 1 || OUT || AV0I2CClock || A/V Encoder (#0) IĀ²C Clock.
 
|-
 
|-
āˆ’
| 24 || OUT || AV1_I2C_CLOCK || A/V Encoder (#1) IĀ²C Clock.
+
| 15 || 1 || OUT || AV0I2CData || A/V Encoder (#0) IĀ²C Data.
 
|-
 
|-
āˆ’
| 25 || I/O || AV1_I2C_DATA || A/V Encoder (#1) IĀ²C Data.
+
| 16 || 1 || I/O || NDEV_LED || Development unit's LED (devkit only).
 
|-
 
|-
āˆ’
| 26 || OUT || MUTE_LAMP || Unknown.
+
| 16 || 1 || OUT || DEBUG0 || Debug Testpoint.
 
|-
 
|-
āˆ’
| 27 || OUT || BT_MODE || BlueTooth mode.
+
| 17 || 1 || OUT || DEBUG1 || Debug Testpoint.
 
|-
 
|-
āˆ’
| 28 || OUT || CCRH_RST || CCRH reset.
+
| 18 || 1 || OUT || DEBUG2 || Debug Testpoint.
 
|-
 
|-
āˆ’
| 29 || OUT || WIFI_MODE || WiFi mode.
+
| 19 || 1 || OUT || DEBUG3 || Debug Testpoint.
 
|-
 
|-
āˆ’
| 30 || OUT || UNKNOWN || Driven low before boot0 SD boot attempt.
+
| 20 || 1 || OUT || DEBUG4 || Debug Testpoint.
 +
|-
 +
| 21 || 1 || OUT || DEBUG5 || Debug Testpoint.
 +
|-
 +
| 22 || 1 || OUT || DEBUG6 || Debug Testpoint.
 +
|-
 +
| 23 || 1 || OUT || DEBUG7 || Debug Testpoint.
 +
|-
 +
| 24 || 1 || OUT || AV1I2CClock || A/V Encoder (#1) IĀ²C Clock.
 +
|-
 +
| 25 || 1 || OUT || AV1I2CData || A/V Encoder (#1) IĀ²C Data.
 +
|-
 +
| 26 || 1 || OUT || MuteLamp || Unknown.
 +
|-
 +
| 27 || 1 || OUT || BlueToothMode || BlueTooth mode.
 +
|-
 +
| 28 || 1 || OUT || CCRHReset || CCR (constant current regulator?) hard reset.
 +
|-
 +
| 29 || 1 || OUT || WiFiMode || WiFi mode.
 +
|-
 +
| 30 || 1 || OUT || SDC0S0Power || SD card (slot 0) power. Driven low before boot0 attempts to read a signed boot1 image from the SD card.
 
|}
 
|}
    
== Register list ==
 
== Register list ==
āˆ’
{{reglist|Latte GPIOs}}
+
{{reglist|Latte GPIOs (group 1)}}
 
{{rla|0x0d8000c0|32|LT_GPIOE_OUT|GPIO Outputs (Espresso access)}}
 
{{rla|0x0d8000c0|32|LT_GPIOE_OUT|GPIO Outputs (Espresso access)}}
 
{{rla|0x0d8000c4|32|LT_GPIOE_DIR|GPIO Direction (Espresso access)}}
 
{{rla|0x0d8000c4|32|LT_GPIOE_DIR|GPIO Direction (Espresso access)}}
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{{rla|0x0d8000f8|32|LT_GPIO_INMIR|GPIO Input Mirror (Starbuck only)}}
 
{{rla|0x0d8000f8|32|LT_GPIO_INMIR|GPIO Input Mirror (Starbuck only)}}
 
{{rla|0x0d8000fc|32|LT_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
 
{{rla|0x0d8000fc|32|LT_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
 +
|}
 +
 +
 +
{{reglist|Latte GPIOs (group 2)}}
 +
{{rla|0x0d800520|32|LT_GPIO2E_OUT|GPIO Outputs (Espresso access)}}
 +
{{rla|0x0d800524|32|LT_GPIOE2_DIR|GPIO Direction (Espresso access)}}
 +
{{rla|0x0d800528|32|LT_GPIOE2_IN|GPIO Inputs (Espresso access)}}
 +
{{rla|0x0d80052c|32|LT_GPIOE2_INTLVL|GPIO Interrupt Levels (Espresso access)}}
 +
{{rla|0x0d800530|32|LT_GPIOE2_INTFLAG|GPIO Interrupt Flags (Espresso access)}}
 +
{{rla|0x0d800534|32|LT_GPIOE2_INTMASK|GPIO Interrupt Masks (Espresso access)}}
 +
{{rla|0x0d800538|32|LT_GPIOE2_INMIR|GPIO Input Mirror (Espresso access)}}
 +
{{rla|0x0d80053c|32|LT_GPIO2_ENABLE|GPIO Enable (Starbuck only)}}
 +
{{rla|0x0d800540|32|LT_GPIO2_OUT|GPIO Outputs (Starbuck only)}}
 +
{{rla|0x0d800544|32|LT_GPIO2_DIR|GPIO Direction (Starbuck only)}}
 +
{{rla|0x0d800548|32|LT_GPIO2_IN|GPIO Inputs (Starbuck only)}}
 +
{{rla|0x0d80054c|32|LT_GPIO2_INTLVL|GPIO Interrupt Levels (Starbuck only)}}
 +
{{rla|0x0d800550|32|LT_GPIO2_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}
 +
{{rla|0x0d800554|32|LT_GPIO2_INTMASK|GPIO Interrupt Masks (Starbuck only)}}
 +
{{rla|0x0d800558|32|LT_GPIO2_INMIR|GPIO Input Mirror (Starbuck only)}}
 +
{{rla|0x0d80055c|32|LT_GPIO2_OWNER|GPIO Owner Select (Starbuck only)}}
 
|}
 
|}
   Line 141: Line 182:     
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the LT_GPIO registers, and that bit is then set in the LT_GPIO_OWNER register, those settings will immediately be visible in the LT_GPIOE registers. There is only one set of data registers, and the LT_GPIO_OWNER register just controls the access that the LT_GPIOE registers have to that data.
 
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the LT_GPIO registers, and that bit is then set in the LT_GPIO_OWNER register, those settings will immediately be visible in the LT_GPIOE registers. There is only one set of data registers, and the LT_GPIO_OWNER register just controls the access that the LT_GPIOE registers have to that data.
 +
----
 +
{{regsimple2|LT_GPIO2_ENABLE|addr=0x0d80053c|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIO2_OUT|addr=0x0d800540|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIO2_DIR|addr=0x0d800544|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIO2_IN|addr=0x0d800548|bits=32|split=24|access=R}}
 +
{{regsimple2|LT_GPIO2_INTLVL|addr=0x0d80054c|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIO2_INTFLAG|addr=0x0d800550|bits=32|split=24|access=R/Z}}
 +
{{regsimple2|LT_GPIO2_INTMASK|addr=0x0d800554|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIO2_INMIR|addr=0x0d800558|bits=32|split=24|access=R}}
 +
{{regsimple2|LT_GPIO2_OWNER|addr=0x0d80055c|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIOE2_OUT|addr=0x0d800520|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIOE2_DIR|addr=0x0d800524|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIOE2_IN|addr=0x0d800528|bits=32|split=24|access=R}}
 +
{{regsimple2|LT_GPIOE2_INTLVL|addr=0x0d80052c|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIOE2_INTFLAG|addr=0x0d800530|bits=32|split=24|access=R/Z}}
 +
{{regsimple2|LT_GPIOE2_INTMASK|addr=0x0d800534|bits=32|split=24|access=R/W}}
 +
{{regsimple2|LT_GPIOE2_INMIR|addr=0x0d800538|bits=32|split=24|access=R}}
 +
These registers are identical to those used for the first GPIO group.
Kyoxid
3

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