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3,272 bytes added ,  20:20, 2 July 2016
gpio stuff
| arm = Full
| ppc = Partial
| base = 0x0d8000c0, 0x0d800520| len = 0x400x80
| bits = 32
| ppcirq = None
}}
The Latte chipset includes at least 29 two groups of general purpose I/O lines with interrupt capability. Two Four sets of registers are provided(two for each group), and the Espresso only has access to one settwo sets. This set accesses These sets access a configurable subset of the IO pins, which the Starbuck can select.
== Pin connections ==
|-
! Bit
! Group
! Direction
! Connection
! Description
|-
| 0 || 1 || IN || SYS_INT RTCSysInt || Power button input (RTCSysInt, FanSpeed and/or ToucanSelect).
|-
| 1 0 || 2 || OUT || DWIFI_MODE FanSpeed || Unknown (DWiFiMode and/or SMCI2CClock)Fan speed.
|-
| 2 0 || OUT 1 || FAN_PWR I/O || ToucanSelect || Fan power, active high "Toucan" select (FanPower and/or SMCI2CDatadevkit only).
|-
| 3 1 || 1 || OUT || DC_DC DWiFiMode || DC/DC converter power (DCDCPwrCnt, DCDCPwrCnt2 and/or CCRIO3), active highDWiFi mode.
|-
| 4 1 || OUT 2 || AV_INT IN || A/V Encoder interrupt SMCI2CClock || SMC (AVInterruptsurface mounted components)?I²C Clock.
|-
| 5 2 || 1 || OUT || ESP10_FIX FanPower || Unknown (ESP10WorkAround and/or CCRIO12)Fan power, active high.
|-
| 6 2 || OUT 2 || AV_RST IN || A/V Encoder reset SMCI2CData || SMC (AVResetsurface mounted components)?I²C Data.
|-
| 7 3 || UNK 1 || UNKNOWN OUT || UnknownDCDCPwrCnt || DC/DC converter power (group 1), active high.
|-
| 8 3 || 2 || OUT || SDC_PWR DCDCPwrCnt2 || Unknown DC/DC converter power (SDC0S0Power and/or PADPDgroup 2), active high.
|-
| 9 3 || UNK 1 || UNKNOWN OUT || CCRIO3 || Unknown.(duplicate?)
|-
| 10 4 || OUT 1 || EEPROM_CS UNK || SEEPROM Chip SelectUNKNOWN || Unknown.
|-
| 11 4 || OUT 2 || EEPROM_SK IN || SEEPROM ClockAVInterrupt || A/V encoder interrupt (from Espresso).
|-
| 12 5 || 1 || OUT || EEPROM_DO ESP10WorkAround || Data to SEEPROMUnknown.
|-
| 13 5 || IN 2 || EEPROM_DI OUT || Data from SEEPROMCCRIO12 || Unknown.
|-
| 14 6 || OUT 1 || AV0_I2C_CLOCK UNK || A/V Encoder (#0) I²C ClockUNKNOWN || Unknown.
|-
| 15 6 || I/O 2 || OUT || AV0_I2C_DATAAVReset || A/V Encoder encoder reset (#0from Espresso) I²C Data.
|-
| 16 7 || OUT 1 || NDEV_LED UNK || DevKit LED?UNKNOWN || Unknown.
|-
| 17 8 || 1 || OUT || DEBUG1 PADPD || Debug?Gamepad power state.
|-
| 18 9 || OUT 1 || DEBUG2 UNK || Debug?UNKNOWN || Unknown.
|-
| 19 10 || 1 || OUT || DEBUG3 EEPROM_CS || Debug?SEEPROM Chip Select.
|-
| 20 11 || 1 || OUT || DEBUG4 EEPROM_SK || Debug?SEEPROM Clock.
|-
| 21 12 || 1 || OUT || DEBUG5 EEPROM_DO || Debug?Data to SEEPROM.
|-
| 22 13 || OUT 1 || DEBUG6 IN || Debug?EEPROM_DI || Data from SEEPROM.
|-
| 23 14 || 1 || OUT || DEBUG7 AV0I2CClock || Debug?A/V Encoder (#0) I²C Clock.
|-
| 24 15 || 1 || OUT || AV1_I2C_CLOCK AV0I2CData || A/V Encoder (#10) I²C ClockData.
|-
| 25 16 || 1 || I/O || AV1_I2C_DATA NDEV_LED || A/V Encoder Development unit's LED (#1devkit only) I²C Data.
|-
| 26 16 || 1 || OUT || MUTE_LAMP DEBUG0 || UnknownDebug Testpoint.
|-
| 27 17 || 1 || OUT || BT_MODE DEBUG1 || BlueTooth modeDebug Testpoint.
|-
| 28 18 || 1 || OUT || CCRH_RST DEBUG2 || CCRH resetDebug Testpoint.
|-
| 29 19 || 1 || OUT || WIFI_MODE DEBUG3 || WiFi modeDebug Testpoint.
|-
| 20 || 1 || OUT || DEBUG4 || Debug Testpoint.|-| 21 || 1 || OUT || DEBUG5 || Debug Testpoint.|-| 22 || 1 || OUT || DEBUG6 || Debug Testpoint.|-| 23 || 1 || OUT || DEBUG7 || Debug Testpoint.|-| 24 || 1 || OUT || AV1I2CClock || A/V Encoder (#1) I²C Clock.|-| 25 || 1 || OUT || AV1I2CData || A/V Encoder (#1) I²C Data.|-| 26 || 1 || OUT || MuteLamp || Unknown.|-| 27 || 1 || OUT || BlueToothMode || BlueTooth mode.|-| 28 || 1 || OUT || CCRHReset || CCR (constant current regulator?) hard reset.|-| 29 || 1 || OUT || WiFiMode || WiFi mode.|-| 30 || 1 || OUT || UNKNOWN SDC0S0Power || SD card (slot 0) power. Driven low before boot0 attempts to read a signed boot1 image from the SD boot attemptcard.
|}
== Register list ==
{{reglist|Latte GPIOs(group 1)}}
{{rla|0x0d8000c0|32|LT_GPIOE_OUT|GPIO Outputs (Espresso access)}}
{{rla|0x0d8000c4|32|LT_GPIOE_DIR|GPIO Direction (Espresso access)}}
{{rla|0x0d8000f8|32|LT_GPIO_INMIR|GPIO Input Mirror (Starbuck only)}}
{{rla|0x0d8000fc|32|LT_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
|}
 
 
{{reglist|Latte GPIOs (group 2)}}
{{rla|0x0d800520|32|LT_GPIO2E_OUT|GPIO Outputs (Espresso access)}}
{{rla|0x0d800524|32|LT_GPIOE2_DIR|GPIO Direction (Espresso access)}}
{{rla|0x0d800528|32|LT_GPIOE2_IN|GPIO Inputs (Espresso access)}}
{{rla|0x0d80052c|32|LT_GPIOE2_INTLVL|GPIO Interrupt Levels (Espresso access)}}
{{rla|0x0d800530|32|LT_GPIOE2_INTFLAG|GPIO Interrupt Flags (Espresso access)}}
{{rla|0x0d800534|32|LT_GPIOE2_INTMASK|GPIO Interrupt Masks (Espresso access)}}
{{rla|0x0d800538|32|LT_GPIOE2_INMIR|GPIO Input Mirror (Espresso access)}}
{{rla|0x0d80053c|32|LT_GPIO2_ENABLE|GPIO Enable (Starbuck only)}}
{{rla|0x0d800540|32|LT_GPIO2_OUT|GPIO Outputs (Starbuck only)}}
{{rla|0x0d800544|32|LT_GPIO2_DIR|GPIO Direction (Starbuck only)}}
{{rla|0x0d800548|32|LT_GPIO2_IN|GPIO Inputs (Starbuck only)}}
{{rla|0x0d80054c|32|LT_GPIO2_INTLVL|GPIO Interrupt Levels (Starbuck only)}}
{{rla|0x0d800550|32|LT_GPIO2_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}
{{rla|0x0d800554|32|LT_GPIO2_INTMASK|GPIO Interrupt Masks (Starbuck only)}}
{{rla|0x0d800558|32|LT_GPIO2_INMIR|GPIO Input Mirror (Starbuck only)}}
{{rla|0x0d80055c|32|LT_GPIO2_OWNER|GPIO Owner Select (Starbuck only)}}
|}
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the LT_GPIO registers, and that bit is then set in the LT_GPIO_OWNER register, those settings will immediately be visible in the LT_GPIOE registers. There is only one set of data registers, and the LT_GPIO_OWNER register just controls the access that the LT_GPIOE registers have to that data.
----
{{regsimple2|LT_GPIO2_ENABLE|addr=0x0d80053c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_OUT|addr=0x0d800540|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_DIR|addr=0x0d800544|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_IN|addr=0x0d800548|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIO2_INTLVL|addr=0x0d80054c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_INTFLAG|addr=0x0d800550|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIO2_INTMASK|addr=0x0d800554|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_INMIR|addr=0x0d800558|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIO2_OWNER|addr=0x0d80055c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_OUT|addr=0x0d800520|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_DIR|addr=0x0d800524|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_IN|addr=0x0d800528|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOE2_INTLVL|addr=0x0d80052c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_INTFLAG|addr=0x0d800530|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIOE2_INTMASK|addr=0x0d800534|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_INMIR|addr=0x0d800538|bits=32|split=24|access=R}}
These registers are identical to those used for the first GPIO group.
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