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Hardware/Memory controller (view source)
Revision as of 00:01, 5 February 2016
, 00:01, 5 February 2016Adding memory controller registers
{{Infobox MMIO
| arm = Full
| base = 0x0d8b0000
| len = ???
| bits = 32
| ppcirq = ???
| latteirq = ???
}}
== Register List ==
{{reglist|Memory Controller}}
{{rld|0x0d8b080c|16|MEM_AMN_RDBIMASK|Unknown}}
{{rld|0x0d8b0854|16|MEM_UNK1|Unknown}}
{{rld|0x0d8b4226|16|MEM_SELF_REFRESH_MODE|Unknown}}
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}
{{rld|0x0d8b422a|16|MEM_FLUSHACK|AHB flush ack}}
{{rld|0x0d8b42c4|16|MEM_WRITE_SEQ_VAL|Unknown}}
{{rld|0x0d8b42c6|16|MEM_WRITE_SEQ_ADDR|Unknown}}
{{rld|0x0d8b42cc|16|MEM_EDRAM_REFRESH_CTRL|Unknown}}
{{rld|0x0d8b42ce|16|MEM_EDRAM_REFRESH_VAL|Unknown}}
{{rld|0x0d8b42d4|16|MEM_MAP_COMPAT_MODE|Unknown}}
{{rld|0x0d8b4300|16|MEM_WRITE_SEQ0_VAL|Unknown}}
{{rld|0x0d8b4302|16|MEM_WRITE_SEQ0_ADDR|Unknown}}
|}
== Register Details ==
| arm = Full
| base = 0x0d8b0000
| len = ???
| bits = 32
| ppcirq = ???
| latteirq = ???
}}
== Register List ==
{{reglist|Memory Controller}}
{{rld|0x0d8b080c|16|MEM_AMN_RDBIMASK|Unknown}}
{{rld|0x0d8b0854|16|MEM_UNK1|Unknown}}
{{rld|0x0d8b4226|16|MEM_SELF_REFRESH_MODE|Unknown}}
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}
{{rld|0x0d8b422a|16|MEM_FLUSHACK|AHB flush ack}}
{{rld|0x0d8b42c4|16|MEM_WRITE_SEQ_VAL|Unknown}}
{{rld|0x0d8b42c6|16|MEM_WRITE_SEQ_ADDR|Unknown}}
{{rld|0x0d8b42cc|16|MEM_EDRAM_REFRESH_CTRL|Unknown}}
{{rld|0x0d8b42ce|16|MEM_EDRAM_REFRESH_VAL|Unknown}}
{{rld|0x0d8b42d4|16|MEM_MAP_COMPAT_MODE|Unknown}}
{{rld|0x0d8b4300|16|MEM_WRITE_SEQ0_VAL|Unknown}}
{{rld|0x0d8b4302|16|MEM_WRITE_SEQ0_ADDR|Unknown}}
|}
== Register Details ==