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{{Infobox MMIO
| arm = Full
| base = 0x0d8b00000x0d8b4000
| len = ???
| bits = 3216
| ppcirq = ???
| latteirq = ???
== Register List ==
{{reglist|Memory Controller}}
{{rld|0x0d8b080c0x0d8b4026|16|MEM_AMN_RDBIMASKMEM_UNK|Unknown}}{{rld|0x0d8b08540x0d8b4200|16|MEM_UNK1MEM_UNK|Unknown}}{{rld|0x0d8b4210|16|MEM_UNK|Unknown}}{{rld|0x0d8b4212|16|MEM_UNK|Unknown}}{{rld|0x0d8b4214|16|MEM_UNK|Unknown}}{{rld|0x0d8b4216|16|MEM_UNK|Unknown}}{{rld|0x0d8b4218|16|MEM_UNK|Unknown}}{{rld|0x0d8b421a|16|MEM_UNK|Unknown}}{{rld|0x0d8b421c|16|MEM_UNK|Unknown}}{{rld|0x0d8b4226|16|MEM_SELF_REFRESH_MODEMEM_REFRESH_FLAG|Unknown}}{{rld|0x0d8b4228|16|MEM_FLUSHREQMEM_FLUSH_MASK|Mask of the AHB connected client to flush requestmemory to/from}}{{rld|0x0d8b422a|16|MEM_FLUSHACKMEM_FLUSH_ACK|AHB flush ackmemory flushing acknowledged state}}{{rld|0x0d8b4268|16|MEM_UNK|Unknown}}{{rld|0x0d8b426a|16|MEM_UNK|Unknown}}{{rld|0x0d8b426c|16|MEM_UNK|Unknown}}{{rld|0x0d8b426e|16|MEM_UNK|Unknown}}{{rld|0x0d8b4270|16|MEM_UNK|Unknown}}{{rld|0x0d8b4272|16|MEM_UNK|Unknown}}{{rld|0x0d8b4274|16|MEM_UNK|Unknown}}{{rld|0x0d8b4276|16|MEM_UNK|Unknown}}{{rld|0x0d8b4278|16|MEM_UNK|Unknown}}{{rld|0x0d8b427a|16|MEM_UNK|Unknown}}{{rld|0x0d8b427c|16|MEM_UNK|Unknown}}{{rld|0x0d8b427e|16|MEM_UNK|Unknown}}{{rld|0x0d8b4280|16|MEM_UNK|Unknown}}{{rld|0x0d8b4282|16|MEM_UNK|Unknown}}{{rld|0x0d8b42a6|16|MEM_UNK|Unknown}}{{rld|0x0d8b42b4|16|MEM_UNK|Unknown}}{{rld|0x0d8b42b6|16|MEM_UNK|Unknown}}{{rld|0x0d8b42ba|16|MEM_UNK|Unknown}}{{rld|0x0d8b42c0|16|MEM_UNK|Unknown}}{{rld|0x0d8b42c2|16|MEM_UNK|Unknown}}{{rld|0x0d8b42c4|16|MEM_WRITE_SEQ_VALMEM_SEQ_REG_VAL|UnknownDDR sequential register's value to read/write}}{{rld|0x0d8b42c6|16|MEM_WRITE_SEQ_ADDRMEM_SEQ_REG_ADDR|UnknownDDR sequential register's address to read/write}}{{rld|0x0d8b42cc|16|MEM_EDRAM_REFRESH_CTRL|UnknownEDRAM refresh settings}}{{rld|0x0d8b42ce|16|MEM_EDRAM_REFRESH_VAL|EDRAM refresh value}}{{rld|0x0d8b42d4|16|MEM_MEM1_COMPAT_MODE|Unknown}}{{rld|0x0d8b42d40x0d8b42d8|16|MEM_MAP_COMPAT_MODEMEM_UNK|Unknown}}{{rld|0x0d8b4300|16|MEM_WRITE_SEQ0_VALMEM_SEQ0_REG_VAL|DDR sequential register's value to read/write}}{{rld|0x0d8b4302|16|MEM_SEQ0_REG_ADDR|DDR sequential register's address to read/write}}{{rld|0x0d8b4400|16|MEM_BLOCK_MEM0_CFG|MEM block protection configuration for MEM0}}{{rld|0x0d8b4402|16|MEM_BLOCK_MEM1_CFG|MEM block protection configuration for MEM1}}{{rld|0x0d8b4404|16|MEM_BLOCK_MEM2_CFG|MEM block protection configuration for MEM2}}{{rld|0x0d8b4406|16|MEM_BLOCK_ERROR_ADDR_LOW|MEM block protection violation's address (low)}}{{rld|0x0d8b4408|16|MEM_BLOCK_ERROR_ADDR_HIGH|MEM block protection violation's address (high)}}{{rld|0x0d8b440e|16|MEM_UNK|Unknown}}{{rld|0x0d8b442a|16|MEM_UNK|Unknown}}{{rld|0x0d8b442c|16|MEM_UNK|Unknown}}{{rld|0x0d8b43020x0d8b44c4|16|MEM_UNK|Unknown}}{{rld|0x0d8b4472|16|MEM_BLOCK_ERROR_CID|MEM block protection violation's client ID}}{{rld|0x0d8b4474|16|MEM_BLOCK_ERROR|MEM block protection violation's state}}{{rld|0x0d8b4494|16|MEM_UNK|Unknown}}{{rld|0x0d8b4492|16|MEM_WRITE_SEQ0_ADDRMEM_UNK|Unknown}}
|}
== Register Details ==
28

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