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Hardware/Memory controller (view source)
Revision as of 01:18, 27 November 2023
, 01:18, 27 November 2023no edit summary
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== Register List ==
== Register List ==
{{reglist|Memory Controller}}
{{reglist|Memory Controller}}
−{{rld|0x0d8b4026|16|MEM_UNK|Unknown}}
+{{rld|0x0d8b4000|16|MEM_MARR0_START|Memory Protection|drs=8}}
+{{rld|0x0d8b4002|16|MEM_MARR0_END}}
+{{rld|0x0d8b4004|16|MEM_MARR1_START}}
+{{rld|0x0d8b4006|16|MEM_MARR1_END}}
+{{rld|0x0d8b4008|16|MEM_MARR2_START}}
+{{rld|0x0d8b400a|16|MEM_MARR2_END}}
+{{rld|0x0d8b400c|16|MEM_MARR3_START}}
+{{rld|0x0d8b400e|16|MEM_MARR3_END}}
+{{rld|0x0d8b4010|16|MEM_MARR_CONTROL|MARR{0-3} permissions}}
+{{rld|0x0d8b4012|16|MEM_CP_BW_DIAL|Bandwidth Dial (Command Processor)}}
+{{rld|0x0d8b4014|16|MEM_TC_BW_DIAL|Bandwidth Dial (Texture Control)}}
+{{rld|0x0d8b4016|16|MEM_PE_BW_DIAL|Bandwidth Dial (Pixel Engine)}}
+{{rld|0x0d8b4018|16|MEM_CPUR_BW_DIAL|Bandwidth Dial (CPU read)}}
+{{rld|0x0d8b401a|16|MEM_CPUW_BW_DIAL|Bandwidth Dial (CPU write)}}
+{{rld|0x0d8b401c|16|MEM_INT_ENBL|MARR interrupt enable}}
+{{rld|0x0d8b401e|16|MEM_INT_STAT|MARR interrupt status}}
+{{rld|0x0d8b4020|16|MEM_INT_CLR|MARR interrupt clear/mask (?)}}
+{{rld|0x0d8b4022|16|MEM_INT_ADDRL|MARR interrupt address (lo bits)}}
+{{rld|0x0d8b4024|16|MEM_INT_ADDRH|MARR interrupt address (hi bits)}}
+{{rld|0x0d8b4026|16|MEM_REFRESH|Memory refresh}}
+{{rld|0x0d8b4028|16|MEM_CONFIG|Memory configuration}}
+{{rld|0x0d8b402a|16|MEM_LATENCY|Memory latency}}
+{{rld|0x0d8b402c|16|MEM_RDTORD|Memory read to read}}
+{{rld|0x0d8b402e|16|MEM_RDTOWR|Memory read to write}}
+{{rld|0x0d8b4030|16|MEM_WRTORD|Memory write to read}}
+{{rld|0x0d8b4032|16|MEM_CP_REQCOUNTH|Memory Request Count (Command Processor) (hi bits)}}
+{{rld|0x0d8b4034|16|MEM_CP_REQCOUNTL|Memory Request Count (Command Processor) (lo bits)}}
+{{rld|0x0d8b4036|16|MEM_TC_REQCOUNTH|Memory Request Count (Texture Control) (hi bits)}}
+{{rld|0x0d8b4038|16|MEM_TC_REQCOUNTL|Memory Request Count (Texture Control) (lo bits)}}
+{{rld|0x0d8b403a|16|MEM_CPUR_REQCOUNTH|Memory Request Count (CPU read) (hi bits)}}
+{{rld|0x0d8b403c|16|MEM_CPUR_REQCOUNTL|Memory Request Count (CPU read) (lo bits)}}
+{{rld|0x0d8b403e|16|MEM_CPUW_REQCOUNTH|Memory Request Count (CPU write) (hi bits)}}
+{{rld|0x0d8b4040|16|MEM_CPUW_REQCOUNTL|Memory Request Count (CPU write) (lo bits)}}
+{{rld|0x0d8b4042|16|MEM_DSP_REQCOUNTH|Memory Request Count (DSP) (hi bits)}}
+{{rld|0x0d8b4044|16|MEM_DSP_REQCOUNTL|Memory Request Count (DSP) (lo bits)}}
+{{rld|0x0d8b4046|16|MEM_IO_REQCOUNTH|Memory Request Count (I/O) (hi bits)}}
+{{rld|0x0d8b4048|16|MEM_IO_REQCOUNTL|Memory Request Count (I/O) (lo bits)}}
+{{rld|0x0d8b404a|16|MEM_VI_REQCOUNTH|Memory Request Count (Video Interface) (hi bits)}}
+{{rld|0x0d8b404c|16|MEM_VI_REQCOUNTL|Memory Request Count (Video Interface) (lo bits)}}
+{{rld|0x0d8b404e|16|MEM_PE_REQCOUNTH|Memory Request Count (Pixel Engine) (hi bits)}}
+{{rld|0x0d8b4050|16|MEM_PE_REQCOUNTL|Memory Request Count (Pixel Engine) (lo bits)}}
+{{rld|0x0d8b4052|16|MEM_RF_REQCOUNTH|Memory Request Count (RF) (hi bits)}}
+{{rld|0x0d8b4054|16|MEM_RF_REQCOUNTL|Memory Request Count (RF) (lo bits)}}
+{{rld|0x0d8b4056|16|MEM_FI_REQCOUNTH|Memory Request Count (FI) (hi bits)}}
+{{rld|0x0d8b4058|16|MEM_FI_REQCOUNTL|Memory Request Count (FI) (lo bits)}}
+{{rld|0x0d8b405a|16|MEM_DRV_STRENGTH|Unknown}}
+{{rld|0x0d8b405c|16|MEM_REFRSH_THHD|Unknown}}
+{{rld|0x0d8b4060|16|MEM_CPUAHMR_REQCOUNTH|Memory Request Count (CPU AHM read) (hi bits)}}
+{{rld|0x0d8b4062|16|MEM_CPUAHMR_REQCOUNTL|Memory Request Count (CPU AHM read) (lo bits)}}
+{{rld|0x0d8b4064|16|MEM_CPUAHMW_REQCOUNTH|Memory Request Count (CPU AHM write) (hi bits)}}
+{{rld|0x0d8b4066|16|MEM_CPUAHMW_REQCOUNTL|Memory Request Count (CPU AHM write) (lo bits)}}
+{{rld|0x0d8b4068|16|MEM_DMAAHMR_REQCOUNTH|Memory Request Count (DMA AHM read) (hi bits)}}
+{{rld|0x0d8b406a|16|MEM_DMAAHMR_REQCOUNTL|Memory Request Count (DMA AHM read) (lo bits)}}
+{{rld|0x0d8b406c|16|MEM_DMAAHMW_REQCOUNTH|Memory Request Count (DMA AHM write) (hi bits)}}
+{{rld|0x0d8b406e|16|MEM_DMAAHMW_REQCOUNTL|Memory Request Count (DMA AHM write) (lo bits)}}
+{{rld|0x0d8b4070|16|MEM_ACC_REQCOUNTH|Memory Request Count (ACC) (hi bits)}}
+{{rld|0x0d8b4072|16|MEM_ACC_REQCOUNTL|Memory Request Count (ACC) (lo bits)}}
+{{rld|0x0d8b4074|16|MEM_DDRREG_ADDR|DDR register offset}}
+{{rld|0x0d8b4076|16|MEM_DDRREG_DATA|DDR register data}}
+{{rld|0x0d8b4078|16|MEM_DRV_PSTRENGTH|Unknown}}
{{rld|0x0d8b4200|16|MEM_COMPAT|Unknown}}
{{rld|0x0d8b4200|16|MEM_COMPAT|Unknown}}
{{rld|0x0d8b4202|16|MEM_PROT_REG|Unknown}}
{{rld|0x0d8b4202|16|MEM_PROT_REG|Unknown}}