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Only the bits set in this register propagate their interrupts to the master [[Hardware/Latte_IRQ_Controller|Latte GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIO_INTFLAG. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~LT_GPIO_OWNERHW_GPIO_OWNER.
This register configures which pins can be controlled by the HW_GPIOB_* registers. A one bit configures the pin for control via the LT_GPIOE HW_GPIOB_* registers, which lets it be accessed by the Espresso. A zero bit restricts access to the HW_GPIO_* registers, which are Starbuck-only. The HW_GPIO_* registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOB_* registers if the corresponding bit is set in the HW_GPIO_OWNER register.


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