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12 bytes removed ,  19:47, 19 November 2019
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{{regsimple2|HW_GPIO_INTMASK|addr=0x0d8000f4|bits=32|split=24|access=R/W}}
Only the bits set in this register propagate their interrupts to the master [[Hardware/Latte_IRQ_Controller|Latte GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIO_INTFLAG. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~HW_GPIO_OWNER.
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{{regsimple2|HW_GPIO_STRAPS|addr=0x0d8000f8|bits=32|split=24|access=R}}
{{regsimple2|HW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_STRAPS|addr=0x0d8000d8|bits=32|split=24|access=R}}
These registers operate identically to their HW_GPIO_* counterparts above, but they only control the pins which have their respective HW_GPIO_OWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the [[Hardware/Latte_IRQ_Controller|Latte GPIOE GPIOB interrupt]] (#10). The generation logic would be HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK, with an implicit AND with HW_GPIO_OWNER since the HW_GPIOB_* registers are already masked with the HW_GPIO_OWNER register.
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIO_* registers, and that bit is then set in the HW_GPIO_OWNER register, those settings will immediately be visible in the HW_GPIOB_* registers. There is only one set of data registers, and the HW_GPIO_OWNER register just controls the access that the HW_GPIOB_* registers have to that data.
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